In the evolution of hybrid integrated circuits for switching systems and high performance processes, as well as other electronic devices, one of the most critical system-packaging needs is the capability of utilizing effectively high input/output (I/O) devices with high speed interconnections. Richard D. Small, Jr. discloses in U.S. Pat. Nos. 4,554,229 and 4,601,972 a multilayer circuit device comprising a substrate having a metallized pattern thereon and a plurality of superposed polymeric dielectric film layers each having a metallized circuit pattern thereon with metallized microvias interconnecting the metallized patterns of one layer with that of at least one other metallized pattern thereunder.
Presently a metallized pattern disclosed in U.S. Pat. Nos. 4,016,050 and 4,109,297 issued to N. G. Lesh et al. and in U.S. Pat. No. 5,288,951 issued to R. P. Frankenthal et al. utilizes composite metallizations. Lesh et al. disclose a composite metallization including, in succession from an insulating substrate, Ti--Cu--Ni--Au and Ti--Pd--Cu--Ni--Au layers, respectively. Frankenthal et al. disclose composite metallization including, in succession from the substrate, Ti--Ti/Pd--Cu--Ni--Au layers. However, whenever these composite metallizations are being used for fabrication of multilayer circuit devices with polymeric dielectric films, their use presents a problem. The problem resides in poor adherence of the polymeric dielectric films to the metal composite metallization, and especially to the top gold layer of the composite.
Improvement in adhesion was attempted by promoting adhesion of the dielectric film to the gold layer in a variety of ways. One of the ways included sputtering of Ti layer on top of the gold or gold and nickel pattern and processing of the Ti layer to convert Ti to titanium oxide that improves the bonding between the metallization and the polymeric dielectric. However, this process is time consuming and costly. Therefore, elimination of at least this adhesion promotion process could lead to simplification of the formation of the multilayer circuit devices and viable cost reduction.